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a
16
Audio/Video 60 MHz 16, G = 2 Crosspoint Switch AD8113
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4 A0 A1 CLK 80-BIT SHIFT REGISTER WITH 5-BIT PARALLEL LOADING 80 PARALLEL LATCH 80 16 DECODE 5:16 DECODERS OUTPUT BUFFER G = +2 16
SET INDIVIDUAL OR RESET ALL OUTPUTS TO "OFF" ENABLE/DISABLE
FEATURES 16 16 High Speed Nonblocking Switch Array Serial or Parallel Programming of Switch Array Serial Data Out Allows Daisy Chaining Control of Multiple 16 16s to Create Larger Switch Arrays Output Disable Allows Connection of Multiple Devices without Loading the Output Bus Complete Solution Buffered Inputs 16 Output Amplifiers Operates on 5 V or 12 V Supplies Low Supply Current of 54 mA Excellent Audio Performance VS = 12 V 10 V Output Swing 0.002% THD @ 20 kHz Max. 20 V p-p (RL = 600 ) Excellent Video Performance VS = 5 V 10 MHz 0.1 dB Gain Flatness 0.1% Differential Gain Error (RL = 1 k ) 0.1 Differential Phase Error (RL = 1 k ) Excellent AC Performance -3 dB Bandwidth 60 MHz Low All Hostile Crosstalk of -83 dB @ 20 kHz Reset Pin Allows Disabling of All Outputs (Connected to a Capacitor to Ground Provides Power-On Reset Capability) 100-Lead LQFP (14 mm 14 mm) APPLICATIONS Analog/Digital Audio Routers Video Routers (NTSC, PAL, S-VIDEO, SECAM) Multimedia Systems Video Conferencing CCTV Surveillance PRODUCT DESCRIPTION
A2 A3 DATA OUT
DATA IN UPDATE CE RESET
AD8113
256
SWITCH MATRIX 16 INPUTS
16 OUTPUTS
The AD8113 is a fully buffered crosspoint switch matrix that operates on 12 V for audio applications and 5 V for video applications. It offers a -3 dB signal bandwidth greater than 60 MHz and channel switch times of less than 60 ns with 0.1% settling for use in both analog and digital audio. The AD8113 operated at 20 kHz has crosstalk performance of -83 dB and isolation of 90 dB. In addition, ground/power pins surround all inputs and outputs to provide extra shielding for operation in the most demanding audio routing applications. The differential gain and differential phase of better than 0.1% and 0.1, respectively, along with 0.1 dB flatness out to 10 MHz, make the AD8113 suitable for many video applications.
The AD8113 includes 16 independent output buffers that can be placed into a disabled state for paralleling crosspoint outputs so that off channel loading is minimized. The AD8113 has a gain of +2. It operates on voltage supplies of 5 V or 12 V while consuming only 34 mA or 31 mA of current, respectively. The channel switching is performed via a serial digital control (which can accommodate daisy-chaining of several devices) or via a parallel control, allowing updating of an individual output without reprogramming the entire array. The AD8113 is packaged in a 100-lead LQFP and is available over the commercial temperature range of 0C to 70C.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD8113-SPECIFICATIONS (T = 25 C, V =
A S
12 V, RL = 600
, unless otherwise noted.)
Min 46 41 Typ 60 60 10 25 10 20 23 100 120 0.1 0.1 0.002 -67 -83 -100 -83 14 12 0.3 0.5 0.5 0.7 0.7 0.7 20 0.3 4 5 3.5 10.5 3 10 55 4.5 10 1.5 5.0 4 50 1 80 50 20 50 34 45 31 50 34 45 31 8 54 38 50 35 54 38 50 35 13 8.5 2.5 Max Unit MHz MHz MHz MHz MHz ns ns V/s V/s % Degrees % dB dB dB dB nV/Hz nV/Hz % % % % % % ppm/C k pF V V V V mA mV V/C V V pF M A ns ns mV p-p mA mA mA mA mA mA mA mA mA
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth
Conditions VOUT = 200 mV p-p, RL = 600 , VS = 12 V VOUT = 200 mV p-p, RL = 150 , VS = 5 V VOUT = 8 V p-p, RL = 600 , VS = 12 V VOUT = 2 V p-p, RL = 150 , VS = 5 V 0.1 dB, VOUT = 200 mV p-p, RL =150 , VS = 5 V VOUT = 2 V p-p, RL = 150 0.1%, 2 V Step, RL =150 , VS = 5 V 2 V Step, RL =150 , VS = 5 V 20 V Step, RL =600 , VS = 12 V NTSC, RL = 1 k, VS = 5 V NTSC, RL = 1 k, VS = 5 V 20 kHz, RL = 600 , 20 V p-p f = 5 MHz, RL =150 , VS = 5 V f = 20 kHz f = 5 MHz, RL =150 , VS = 5 V, One Channel f = 20 kHz, One Channel 20 kHz 0.1 MHz-10 MHz No Load, VS = 12 V, VOUT = 8 V RL = 600 , VS = 12 V RL = 150 , VS = 5 V No Load, Channel-to-Channel RL = 600 , Channel-to-Channel RL = 150 , Channel-to-Channel
Gain Flatness Propagation Delay Settling Time Slew Rate NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Total Harmonic Distortion Crosstalk, All Hostile Off Isolation Input Voltage Noise DC PERFORMANCE Gain Error
Gain Matching
3.5
Gain Temperature Coefficient OUTPUT CHARACTERISTICS Output Resistance Output Capacitance Output Voltage Swing Enabled Disabled Disabled VS = 5 V, No Load VS = 12 V, No Load IOUT = 20 mA, VS = 5 V IOUT = 20 mA, VS = 12 V RL = 0 All Configurations Temperature Coefficient No Load, VS = 5 V VS = 12 V Any Switch Configuration Any Number of Enabled Inputs
3.4 3.2 10.3 2.7 9.8
Short Circuit Current INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) POWER SUPPLIES Supply Current
1.6
50% Update to 1% Settling
AVCC Outputs Enabled, No Load, V S = 12 V AVCC Outputs Disabled, VS = 12 V AVCC Outputs Enabled, No Load, V S = 5 V AVCC Outputs Disabled, VS = 5 V AVEE Outputs Enabled, No Load, V S = 12 V AVEE Outputs Disabled, V S = 12 V AVEE Outputs Enabled, No Load, V S = 5 V AVEE Outputs Disabled, V S = 5 V DVCC Outputs Enabled, No Load
-2-
REV. A
AD8113
Parameter DYNAMIC PERFORMANCE Supply Voltage Range Conditions AVCC AVEE DVCC DC f = 100 kHz f = 1 MHz Operating (Still Air) Operating (Still Air) Min 4.5 -12.6 4.5 75 Typ Max 12.6 -4.5 5.5 80 60 40 0 to 70 40 Unit V V V dB dB dB C C/W
PSRR
OPERATING TEMPERATURE RANGE Temperature Range JA
Specifications subject to change without notice.
TIMING CHARACTERISTICS (Serial)
Parameter Serial Data Setup Time CLK Pulsewidth Serial Data Hold Time CLK Pulse Separation, Serial Mode CLK to UPDATE Delay UPDATE Pulsewidth CLK to DATA OUT Valid, Serial Mode Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz, Serial Mode CLK, UPDATE Rise and Fall Times RESET Time
Specifications subject to change without notice.
Symbol t1 t2 t3 t4 t5 t6 t7
Limit Min 20 100 20 100 0 50
Typ
Max
Unit ns ns ns ns ns ns ns ns s ns ns
200 50 16 100 200
1 CLK 0 1 DATA IN 0 1 = LATCHED UPDATE 0 = TRANSPARENT
t2
t4
LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE OUT7 (D3) OUT00 (D0)
t1
t3
OUT7 (D4)
t5
TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL
t6
t7
DATA OUT
Figure 1. Timing Diagram, Serial Mode
Table I. Logic Levels
VIH RESET, SER/PAR CLK, DATA IN, CE, UPDATE 2.0 V min VIL RESET, SER/PAR CLK, DATA IN, CE, UPDATE 0.8 V max VOH VOL IIH RESET, SER/PAR CLK, DATA IN, CE, UPDATE 20 A max IIL RESET, SER/PAR CLK, DATA IN, CE, UPDATE -400 A min IOH IOL
DATA OUT 2.7 V min
DATA OUT 0.5 V max
DATA OUT -400 A max
DATA OUT 3.0 mA min
REV. A
-3-
AD8113 TIMING CHARACTERISTICS (Parallel)
Parameter Data Setup Time CLK Pulsewidth Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulsewidth Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and Fall Times RESET Time
Specifications subject to change without notice.
t2
1 CLK 0
Symbol t1 t2 t3 t4 t5 t6
Limit Min 20 100 20 100 0 50
Max
Unit ns ns ns ns ns ns ns ns ns
50 100 200
t4
t1
D0-D4 A0-A2 1 0
t3
t5
1 = LATCHED UPDATE 0 = TRANSPARENT
t6
Figure 2. Timing Diagram, Parallel Mode
Table II. Logic Levels
VIH RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3 CE, UPDATE 2.0 V min VIL VOH VOL IIH RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3 CE, UPDATE 20 A max IIL RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3 CE, UPDATE -400 A min IOH IOL
RESET, SER/PAR CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3 CE, UPDATE DATA OUT DATA OUT 0.8 V max 2.7 V min 0.5 V max
DATA OUT DATA OUT -400 A max 3.0 mA min
-4-
REV. A
AD8113
ABSOLUTE MAXIMUM RATINGS 1 POWER DISSIPATION
Analog Supply Voltage (AVCC - AVEE) . . . . . . . . . . . . 26.0 V Digital Supply Voltage (DVCC - DGND) . . . . . . . . . . . . . . 6 V Ground Potential Difference (AGND - DGND) . . . . . 0.5 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 3.1 W Analog Input Voltage3 . . . . . . . . . . . Maintain Linear Output Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . DVCC Output Voltage (Disabled Output) . . . . . . . . . . . . . . . . . . . . (AVCC - 1.5 V) to (AVEE + 1.5 V) Output Short-Circuit Duration . . . . . . . . . . . . . . Momentary Storage Temperature Range . . . . . . . . . . . . -65C to +125C Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300C
NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Specification is for device in free air (T = 25C): A 100-lead plastic LQFP (ST): JA = 40C/W. 3 To avoid differential input breakdown, in no case should one-half the output voltage (1/2 V OUT) and any input voltage be greater than 10 V potential differential. See output voltage swing specification for linear output range.
The AD8113 is operated with 5 V to 12 V supplies and can drive loads down to 150 ( 5 V) or 600 ( 12 V), resulting in a large range of possible power dissipations. For this reason, extra care must be taken derating the operating conditions based on ambient temperature. Packaged in a 100-lead LQFP, the AD8113 junction-to-ambient thermal impedance (JA) is 40C/W. For long-term reliability, the maximum allowed junction temperature of the plasticencapsulated die should not exceed 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. The following curve shows the range of allowed power dissipations that meet these conditions over the commercial range of ambient temperatures.
4.0 TJ = 150 C
MAXIMUM POWER - Watts
3.5
3.0
2.5
2.0 0 10 20 30 40 50 AMBIENT TEMPERATURE - C 60 70
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ORDERING GUIDE Model AD8113JST AD8113-EVAL Temperature Range 0C to 70C Package Description 100-Lead Plastic LQFP (14 mm x 14 mm) Evaluation Board Package Option ST-100
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8113 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-5-
AD8113
Table III. Operation Truth Table
CE 1 0
UPDATE X 1
CLK X f
DATA IN X Data i
DATA OUT X Data i-80
RESET X 1
SER/ PAR X 0
Operation/Comment No change in logic. The data on the serial DATA IN line is loaded into serial register. The first bit clocked into the serial register appears at DATA OUT 80 clocks later. The data on the parallel data lines, D0-D4, are loaded into the 80-bit serial shift register location addressed by A0-A3. Data in the 80-bit shift register transfers into the parallel latches that control the switch array. Latches are transparent. Asynchronous operation. All outputs are disabled. Remainder of logic is unchanged.
0
1
f X
D0 . . . D4, A0 . . . A3 X
NA in Parallel Mode X
1
1
0
0
1
X
X
X
X
X
X
0
X
PARALLEL DATA (OUTPUT ENABLE) SER/PAR
D0 D1 D2 D3 D4
S D1
S D1 DQ CLK Q D0 DQ CLK
S D1 Q D0 DQ CLK
S D1 Q D0 DQ CLK
S D1 Q DQ D0 CLK
S D1 Q D0 DQ CLK
S D1 Q DQ D0 CLK
S D1 Q D0 DQ CLK
S D1 Q D0 DQ CLK
S D1 Q D0 DQ CLK
S D1 Q D0 DQ CLK
S D1 Q D0 DQ CLK
DATA IN (SERIAL)
Q D0
DATA OUT
CLK CE UPDATE
OUT0 EN
OUTPUT ADDRESS
OUT1 EN OUT2 EN OUT3 EN OUT4 EN OUT5 EN
A0 A1
4 TO 16 DECODER
A2 A3
OUT6 EN OUT7 EN OUT8 EN OUT9 EN OUT10 EN OUT11 EN OUT12 EN OUT13 EN OUT14 EN OUT15 EN
LE D OUT0 B0 Q
LE D OUT0 B1 Q
LE D OUT0 B2 Q
LE D OUT0 B3 Q
LE D OUT0 EN CLR Q
LE D OUT1 B0 Q
LE D OUT14 EN CLR Q
LE D OUT15 B0 Q
LE D OUT15 B1 Q
LE D OUT15 B2 Q
LE D OUT15 B3 Q
LE D OUT15 EN CLR Q
RESET (OUTPUT ENABLE) DECODE 256 SWITCH MATRIX 16 OUTPUT ENABLE
Figure 4. Logic Diagram
-6-
REV. A
AD8113
PIN FUNCTION DESCRIPTIONS Mnemonic INxx DATA IN CLK DATA OUT UPDATE RESET CE SER/PAR OUTyy AGND DVCC DGND AVEE AVCC AVCCxx/yy AVEExx/yy A0 A1 A2 A3 D0 D1 D2 D3 D4 NC Pin Numbers 58, 60, 62, 64, 66, 68, 70, 72, 4, 6, 8, 10, 12, 14, 16, 18 96 97 98 95 100 99 94 53, 51, 49, 47, 45, 43, 41, 39, 37, 35, 33, 31, 29, 27, 25, 23 3, 5, 7, 9, 11, 13, 15, 17, 19, 57, 59, 61, 63, 65, 67, 69, 71, 73 1, 75 2, 74 20, 56 21, 55 54, 50, 46, 42, 38, 34, 30, 26, 22 52, 48, 44, 40, 36, 32, 28, 24 84 83 82 81 80 79 78 77 76 85-93
VCC ESD INPUT ESD ESD AVEE
Pin Description Analog Inputs; xx = Channel Numbers 00 through 15. Serial Data Input, TTL Compatible. Clock, TTL Compatible. Falling Edge Triggered. Serial Data Out, TTL Compatible. Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data latched when High. Disable Outputs, Active Low. Chip Enable, Enable Low. Must be low to clock in and latch data. Selects Serial Data Mode, Low or Parallel Data Mode, High. Must be connected. Analog Outputs yy = Channel Numbers 00 Through 15. Analog Ground for Inputs and Switch Matrix. Must be connected. 5 V for Digital Circuitry. Ground for Digital Circuitry. -5 V for Inputs and Switch Matrix. 5 V for Inputs and Switch Matrix. 5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected. -5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected. Parallel Data Input, TTL Compatible (Output Select LSB). Parallel Data Input, TTL Compatible (Output Select). Parallel Data Input, TTL Compatible (Output Select). Parallel Data Input, TTL Compatible (Output Select MSB). Parallel Data Input, TTL Compatible (Input Select LSB). Parallel Data Input, TTL Compatible (Input Select). Parallel Data Input, TTL Compatible (Input Select). Parallel Data Input, TTL Compatible (Input Select MSB). Parallel Data Input, TTL Compatible (Output Enable). No Connect.
VCC ESD OUTPUT
RESET ESD VCC ESD 20k
AVEE
DGND
a. Analog Input
b. Analog Output
c. Reset Input
VCC ESD INPUT ESD
VCC 2k ESD OUTPUT ESD
DGND
DGND
d. Logic Input
e. Logic Output
Figure 5. I/O Schematics
REV. A
-7-
AD8113
PIN CONFIGURATION
98 DATA OUT 97 CLK
100 RESET 99 CE
96 DATA IN 95 UPDATE 94 SER/PAR
93 NC 92 NC
86 NC 85 NC
88 NC 87 NC
89 NC
91 NC 90 NC
DVCC DGND AGND IN08 AGND IN09 AGND IN10
1 2 3 4 5 6 7 8
PIN 1 IDENTIFIER
78 D2 77 D3
81 A3 80 D0
84 A0 83 A1 82 A2
79 D1
76 D4
75 DVCC 74 DGND 73 AGND 72 IN07 71 AGND 70 IN06 69 AGND 68 IN05 67 AGND 66 IN04 65 AGND 64 IN03 63 AGND 62 IN02 61 AGND 60 IN01 59 AGND 58 IN00 57 AGND 56 AVEE 55 AVCC 54 AVCC00 53 OUT00 52 AVEE00/01 51 OUT01
AGND 9 IN11 10 AGND 11 IN12 12 AGND 13 IN13 14 AGND 15 IN14 16 AGND 17 IN15 18 AGND 19 AVEE 20 AVCC 21 AVCC15 22 OUT15 23 AVEE14/15 24 OUT14 25
AD8113
TOP VIEW (Not to Scale)
AVEE06/07 40 OUT06 41
AVCC05/06 42 OUT05 43
AVEE04/05 44
OUT04 45 AVCC03/04 46
OUT03 47 AVEE02/03 48
OUT13 27 AVEE12/13 28
OUT12 29
AVCC11/12 30 OUT11 31
AVEE10/11 32 OUT10 33
AVCC09/10 34
OUT02 49
OUT08 37 AVCC07/08 38
NC = NO CONNECT
AVCC13/14 26
-8-
AVCC01/02 50
OUT09 35 AVEE08/09 36
OUT07 39
REV. A
Typical Performance Characteristics-AD8113
3.0
3.0
0.0
GAIN - dB GAIN - dB
0.0
-3.0
-3.0
-6.0 0.01
0.1
1 FREQUENCY - MHz
10
100
-6.0 0.1
1 10 FREQUENCY - MHz
100
TPC 1. Small Signal Bandwidth, VS = 5 V, RL = 150 , VOUT = 200 mV p-p
TPC 4. Small Signal Bandwidth, VS = 12 V, RL = 600 , VOUT = 200 mV p-p
0.3
0.3
0.2
GAIN FLATNESS - dB GAIN FLATNESS - dB
0.2
0.1
0.1
0.0
0.0
-0.1
-0.1
-0.2
-0.2
-0.3 0.1
1 10 FREQUENCY - MHz
100
-0.3 0.1
1 10 FREQUENCY - MHz
100
TPC 2. Small Signal Gain Flatness, V S = 5 V, RL = 150 , VOUT = 200 mV p-p
TPC 5. Small Signal Gain Flatness, VS = 12 V, RL = 600 , VOUT = 200 mV p-p
3.0
3.0
0.0
0.0
GAIN - dB
-3.0
GAIN - dB
-3.0 -6.0 0.1 1 10 FREQUENCY - MHz 100 -6.0 0.1
1 10 FREQUENCY - MHz
100
TPC 3. Large Signal Bandwidth, VS = 5 V, RL = 150 , VOUT = 2 V p-p
TPC 6. Large Signal Bandwidth, VS = 12 V, RL = 600 , VOUT = 8 V p-p
REV. A
-9-
AD8113
0.3
0.3
0.2
GAIN FLATNESS - dB
0.2
GAIN FLATNESS - dB
0.1
0.1
0.0
0.0
-0.1
-0.1
-0.2
-0.2
-0.3 0.1
1 10 FREQUENCY - MHz
100
-0.3 0.1
1 FREQUENCY - MHz
10
TPC 7. Large Signal Gain Flatness, VS = 5 V, RL = 150 , VOUT = 2 V p-p
TPC 10. Large Signal Gain Flatness, VS = 12 V, RL = 600 , VOUT = 8 V p-p
-40 ALL HOSTILE -50
-30
-40 ALL HOSTILE
CROSSTALK - dB
CROSSTALK - dB
-60 ADJACENT -70
-50
-60 ADJACENT -70
-80
-90
-80
-100 0.1
1 10 FREQUENCY - MHz
100
-90 0.01
0.1
1 FREQUENCY - MHz
10
100
TPC 8. Crosstalk vs. Frequency, VS = 5 V, RL = 150 , VOUT = 2 V p-p
TPC 11. Crosstalk vs. Frequency, VS = 12 V, RL = 600 , VOUT = 20 V p-p
-50
-70 -75
-60
DISTORTION - dBc
-70 2ND HARMONIC -80
DISTORTION - dBc
-80 -85 -90 -95
2ND HARMONIC
-90
-100 3RD HARMONIC -110 0.001
-100 3RD HARMONIC -105 0.001
0.01
0.1 1 FREQUENCY - MHz
10
100
0.01 0.1 FREQUENCY - MHz
1
TPC 9. Distortion vs. Frequency, VS = 5 V, RL = 150 , VOUT = 2 V p-p
TPC 12. Distortion vs. Frequency, VS = 12 V, RL = 600 , VOUT = 20 V p-p
-10-
REV. A
AD8113
300 250
INPUT
CAP LOAD - pF
200
150
VS = 12V RL = 600 VS = 5V RL = 150
0.1%/DIV
OUTPUT - INPUT 2 OUTPUT
100
50
0 0 5 10 15 20 25 SERIES RESISTANCE - 30 35
0
5
10
15
20
25 5ns/DIV
30
35
40
45
50
TPC 13. Cap Load vs. Series Resistance for Less than 30% Overshoot
TPC 16. Settling Time to 0.1%, 2 V Step, VS = 5 V, RL = 150
10k
10k
1k
1k
IMPEDANCE -
100
IMPEDANCE -
100
10
10
1 0.1
1
10 FREQUENCY - MHz
100
1000
1 0.1
1
10 FREQUENCY - MHz
100
1000
TPC 14. Disabled Output Impedance vs. Frequency, VS = 5 V
TPC 17. Disabled Output Impedance vs. Frequency, VS = 12 V
1k
1k
100
IMPEDANCE -
100
IMPEDANCE -
10
10
1
1
0.1 0.1
1
10 FREQUENCY - MHz
100
1000
0.1 0.1
1
10 FREQUENCY - MHz
100
1000
TPC 15. Enabled Output Impedance vs. Frequency, VS = 5 V
TPC 18. Enabled Output Impedance vs. Frequency, VS = 12 V
REV. A
-11-
AD8113
0 -10 -20 -30
PSRR - dB
0
-20
-40 -50
+PSRR -PSRR
PSRR - dB
-40 +PSRR -60 -PSRR
-60 -70 -80 -90 0.01
-100 0.01 -80
1 0.1 FREQUENCY - MHz
10
0.1 1 FREQUENCY - MHz
10
TPC 19. PSRR vs. Frequency, VS = 5 V
TPC 22. PSRR vs. Frequency, VS = 12 V
160 140
0
-20
120
OFF ISOLATION - dB
NOISE - nV/ Hz
-40 VS = 12V RL = 600 VOUT = 8V p-p
100 80 60 40
-60
-80 VS = 5V RL = 150 VOUT = 2V p-p 1 10 FREQUENCY - MHz 100
-100
20 0 10
-120 0.1
100
1k
10k 100k FREQUENCY - Hz
1M
10M
TPC 20. Noise vs. Frequency
TPC 23. Off Isolation vs. Frequency
50mV/DIV
50mV/DIV
50ns/DIV
100ns/DIV
TPC 21. Small Signal Pulse Response, VS = 5 V, RL = 150
TPC 24. Small Signal Pulse Response, VS = 12 V, RL = 600
-12-
REV. A
AD8113
500mV/DIV
5V/DIV
100ns/DIV
100ns/DIV
TPC 25. Large Signal Pulse Response, VS = 5 V, RL = 150
TPC 28. Large Signal Pulse Response, VS = 12 V, RL = 600
2V/DIV
2V/DIV
10V/DIV
100ns/DIV
100ns/DIV
TPC 26. Switching Time, VS = 5 V, RL = 150
TPC 29. Switching Time, VS = 12 V, RL = 600
1V/DIV
1V/DIV
OUTPUT 20mV/DIV
20mV/DIV
OUTPUT
100ns/DIV
100ns/DIV
TPC 27. Switching Transient, VS = 5 V, RL = 150
TPC 30. Switching Transient, VS = 12 V, RL = 600
REV. A
-13-
AD8113
THEORY OF OPERATION
The AD8113 is a gain-of-two crosspoint array with 16 outputs, each of which can be connected to any one of 16 inputs. Organized by output row, 16 switchable transconductance stages are connected to each output buffer in the form of a 16-to-1 multiplexer. Each of the 16 rows of transconductance stages are wired in parallel to the 16 input pins, for a total array of 256 transconductance stages. Decoding logic for each output selects one (or none) of the transconductance stages to drive the output stage. The transconductance stages are NPN input differential pairs, sourcing current into the folded cascode output stage. The compensation networks and emitter follower output buffers are in the output stage. Voltage feedback sets the gain at +2. When operated with 12 V supplies, this architecture provides 10 V drive for 600 audio loads with extremely low distortion (<0.002%) at audio frequencies. Provided the supplies are lowered to 5 V (to limit power consumption), the AD8113 can drive reverse-terminated video loads, swinging 3.0 V into 150 . Disabling unused outputs and transconductance stages minimizes on-chip power consumption. Features of the AD8113 facilitate the construction of larger switch matrices. The unused outputs can be disabled, leaving only a feedback network resistance of 4 k on the output. This allows multiple ICs to be bused together, provided the output load impedance is greater than minimum allowed values. Because no additional input buffering is necessary, high input resistance and low input capacitance are easily achieved without additional signal degradation. The AD8113 inputs have a unique bias current compensation scheme that overcomes a problem common to transconductance input array architectures. Typically, input bias current increases as more and more transconductance stages connected to the same input are turned on. Anywhere from zero to 16 transconductance stages can be sharing one input pin, so there is a varying amount of bias current supplied through the source impedance driving
the input. For audio systems with larger source impedances, this has the potential of creating large offset voltages, audible as pops when switching between channels. The AD8113 samples and cancels the input bias current contributions from each transconductance stage so that the residual bias current is nominally zero regardless of the number of enabled inputs. Due to the flexibility in allowed supply voltages, internal crosstalk isolation clamps have variable bias levels. These levels were chosen to allow for the necessary input range to accommodate the full output swing with a gain of two. Overdriving the inputs beyond the device's linear range will eventually forward bias these clamps, increasing power dissipation. The valid input range for 12 V supplies is 5 V. The valid input range for 5 V supplies is 1.5 V. When outputs are disabled and being driven externally, the voltage applied to them should not exceed the valid output swing range for the AD8113. Exceeding 10.5 V on the outputs of the AD8113 may apply a large differential voltage on the unused transconductance stages and should be avoided. A flexible TTL compatible logic interface simplifies the programming of the matrix. Either parallel or serial loading into a first rank of latches programs each output. A global latch simultaneously updates all outputs. In serial mode, a serial-out pin allows devices to be daisy chained together for single pin programming of multiple ICs. A power-on reset pin is available to avoid bus conflicts by disabling all outputs. Regardless of the supply voltage applied to the AVCC and AVEE pins, the digital logic requires 5 V on the DVCC pin with respect to DGND. In order for the digital-to-analog interface to work properly, DVCC must be at least 7 V above AVEE. Finally, internal ESD protection diodes require that the DGND and AGND pins be at the same potential.
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REV. A
AD8113
CALCULATION OF POWER DISSIPATION
4.0 TJ = 150 C
MAXIMUM POWER - Watts
QNPN AVCC IO, QUIESCENT VOUTPUT RF 4k IOUTPUT AGND IO, QUIESCENT
3.5
QPNP
3.0
AVEE
Figure 7. Simplified Output Stage
2.5
An example: AD8113, in an ambient temperature of 70C, with all 16 outputs driving 6 V rms into 600 loads. Power supplies are 12 V.
0 10 20 30 40 50 AMBIENT TEMPERATURE - C 60 70
2.0
Step 1. Calculate power dissipation of AD8113 using data sheet quiescent currents. PD, QUIESCENT = (AVCC x IAVCC) + (AVEE x IAVEE) + (DVCC x IDVCC ) PD, QUIESCENT = (12 V x 54 mA) + (-12 V x -54 mA) + (5 V x 13 mA) Step 2. Calculate power dissipation from loads. PD, OUTPUT = (AVCC - VOUTPUT, RMS) x IOUTPUT, RMS + VOUTPUT2/4 k PD, OUTPUT = (12 V - 6 V) x 6 V/600 + (6 V )2/4 k = 69 mW There are 16 outputs, so nPD, OUTPUT = 16 x 69 mW = 1.1 W Step 3. Subtract quiescent output current for number of loads (assumes output voltage >> 0.5 V). PDQ, OUTPUT = (AVCC - AVEE) x IO, QUIESCENT PDQ, OUTPUT = (12 V - (-12 V)) x 0.67 mA = 16 mW There are 16 outputs, so nPD, OUTPUT = 16 x 16 mW = 0.3 W Step 4. Verify that power dissipation does not exceed maximum allowed value. PD, ON-CHIP = PD, QUIESCENT + nPD, OUTPUT - nPDQ, OUTPUT PD, ON-CHIP = 1.3 W + 1.1 W - 0.3 W = 2.1 W From the figure or the equation, this power dissipation is below the maximum allowed dissipation for all ambient temperatures approaching 70C. NOTE: It can be shown that for a dual supply of a, a Class AB output stage dissipates maximum power into a grounded load when the output voltage is a/2. So for a 12 V supply, the above example demonstrates the worst-case power dissipation into 600 . It can be seen from this example that the minimum load resistance for 12 V operation is 600 (for full rated operating temperature range). For larger safety margins, when the output signal is unknown, loads of 1 k and greater are recommended. When operating with 5 V supplies, this load resistance may be lowered to 150 .
Figure 6. Maximum Power Dissipation vs. Ambient Temperature
The above curve was calculated from
PD , MAX
(TJUNCTION , MAX - TAMBIENT ) =
JA
As an example, if the AD8113 is enclosed in an environment at 50C (TA), the total on-chip dissipation under all load and supply conditions must not be allowed to exceed 2.5 W. When calculating on-chip power dissipation, it is necessary to include the rms current being delivered to the load, multiplied by the rms voltage drop on the AD8113 output devices. The dissipation of the on-chip, 4 k feedback resistor network must also be included. For a sinusoidal output, the on-chip power dissipation due to the load and feedback network can be approximated by
PD , MAX = ( AVCC - VOUTPUT, RMS ) x IOUTPUT, RMS VOUTPUT, RMS 2 + 4 k
For nonsinusoidal output, the power dissipation should be calculated by integrating the on-chip voltage drop multiplied by the load current over one period. The user may subtract the quiescent current for the Class AB output stage when calculating the loaded power dissipation. For each output stage driving a load, subtract a quiescent power according to PD , OUTPUT = ( AVCC - AVEE ) x IO, QUIESCENT For the AD8113, IO, QUIESCENT = 0.67 mA. For each disabled output, the quiescent power supply current in AVCC and AVEE drops by approximately 1.25 mA, although there is a power dissipation in the on-chip feedback resistors if the disabled output is being driven from an external source.
REV. A
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AD8113
SHORT-CIRCUIT OUTPUT CONDITIONS
Although there is short-circuit current protection on the AD8113 outputs, the output current can reach values of 55 mA into a grounded output. Any sustained operation with even one shorted output will exceed the maximum die temperature and can result in device failure (see Absolute Maximum Ratings).
APPLICATIONS
cycle, significant time savings can be realized by using parallel programming. One important consideration in using parallel programming is that the RESET signal DOES NOT RESET ALL REGISTERS in the AD8113. When taken LOW, the RESET signal will only set each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs will not be active at the same time. After initial power-up, the internal registers in the device will generally have random data, even though the RESET signal has been asserted. If parallel programming is used to program one output, then that output will be properly programmed, but the rest of the device will have a random program state depending on the internal register content at power-up. Therefore, when using parallel programming, it is essential that ALL OUTPUTS BE PROGRAMMED TO A DESIRED STATE AFTER POWER-UP. This will ensure that the programming matrix is always in a known state. From then on, parallel programming can be used to modify a single output or more at a time. In similar fashion, if both CE and UPDATE are taken LOW after initial power-up, the random power-up data in the shift register will be programmed into the matrix. Therefore, in order to prevent the crosspoint from being programmed into an unknown state, DO NOT APPLY LOW LOGIC LEVELS TO BOTH CE AND UPDATE AFTER POWER IS INITIALLY APPLIED. Programming the full shift register one time to a desired state, by either serial or parallel programming after initial power-up, will eliminate the possibility of programming the matrix to an unknown state. To change an output's programming via parallel programming, SER/PAR and UPDATE should be taken HIGH and CE should be taken LOW. The CLK signal should be in the HIGH state. The 4-bit address of the output to be programmed should be put on A0-A3. The first four data bits (D0-D3) should contain the information that identifies the input that gets programmed to the output that is addressed. The fifth data bit (D4) will determine the enabled state of the output. If D4 is LOW (output disabled), then the data on D0-D3 does not matter. After the desired address and data signals have been established, they can be latched into the shift register by a high to low transition of the CLK signal. The matrix will not be programmed, however, until the UPDATE signal is taken low. It is thus possible to latch in new data for several or all of the outputs first via successive negative transitions of CLK while UPDATE is held HIGH, and then have all the new data take effect when UPDATE goes LOW. This is the technique that should be used when programming the device for the first time after power-up when using parallel programming.
POWER-ON RESET
The AD8113 has two options for changing the programming of the crosspoint matrix. In the first option a serial word of 80 bits can be provided that will update the entire matrix each time. The second option allows for changing a single output's programming via a parallel interface. The serial option requires fewer signals, but more time (clock cycles) for changing the programming, while the parallel programming technique requires more signals, but can change a single output at a time and requires fewer clock cycles to complete programming.
Serial Programming
The serial programming mode uses the device pins CE, CLK, DATA IN, UPDATE, and SER/PAR. The first step is to assert a LOW on SER/PAR in order to enable the serial programming mode. CE for the chip must be LOW to allow data to be clocked into the device. The CE signal can be used to address an individual device when devices are connected in parallel. The UPDATE signal should be high during the time that data is shifted into the device's serial port. Although the data will still shift in when UPDATE is LOW, the transparent, asynchronous latches will allow the shifting data to reach the matrix. This will cause the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATA IN is clocked in at every down edge of CLK. A total of 80 bits must be shifted in to complete the programming. For each of the 16 outputs, there are four bits (D0-D3) that determine the source of its input followed by one bit (D4) that determines the enabled state of the output. If D4 is LOW (output disabled), the four associated bits (D0-D3) do not matter, because no input will be switched to that output. The most-significant-output-address data is shifted in first, then following in sequence until the least-significant-output-address data is shifted in. At this point UPDATE can be taken low, which will cause the programming of the device according to the data that was just shifted in. The UPDATE registers are asynchronous and when UPDATE is low (and CE is low), they are transparent. If more than one AD8113 device is to be serially programmed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain. All of the CLK, CE, UPDATE, and SER/PAR pins should be connected in parallel and operated as described above. The serial data is input to the DATA IN pin of the first device of the chain, and it will ripple through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence will be 80 bits times the number of devices in the chain.
Parallel Programming
When using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. In fact, parallel programming allows the modification of a single output at a time. Since this takes only one CLK/UPDATE
When powering up the AD8113, it is usually desirable to have the outputs come up in the disabled state. The RESET pin, when taken LOW, will cause all outputs to be in the disabled state. However, the RESET signal DOES NOT RESET ALL REGISTERS in the AD8113. This is important when operating in the parallel programming mode. Please refer to that section for information about programming internal registers after power-up. Serial programming will program the entire matrix each time, so no special considerations apply. REV. A
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AD8113
Since the data in the shift register is random after power-up, it should not be used to program the matrix, or the matrix can enter unknown states. To prevent this, DO NOT APPLY LOGIC LOW SIGNALS TO BOTH CE AND UPDATE INITIALLY AFTER POWER-UP. The shift register should first be loaded with the desired data, and then UPDATE can be taken LOW to program the device. The RESET pin has a 20 k pull-up resistor to DVCC that can be used to create a simple power-up reset circuit. A capacitor from RESET to ground will hold RESET low for some time while the rest of the device stabilizes. The low condition will cause all the outputs to be disabled. The capacitor will then charge through the pull-up resistor to the high state, thus allowing full programming capability of the device.
SPECIFYING AUDIO LEVELS
Figure 8 shows a typical input with a divide-by-two input divider that will create a unity gain channel. The circuit uses 1 k resistors to form the divider. These resistors need to be high enough so they will not overload the drive circuit. But if they are too high, they will generate an offset voltage due to the input bias current that flows through them. Larger resistors will also increase the thermal noise of the channel. This circuit can handle inputs that swing up to 10 V when the AD8113 operates on analog supplies of 12 V. After the divider, the maximum voltage will be 5 V at the input. This maximum input amplitude will be 10 V at the output after the gain-of-two of the channel.
VIDEO SIGNALS
Several methods are used to specify audio levels. A level is actually a power measurement, which requires not just a voltage measurement, but also a reference impedance. Traditionally both 150 and 600 have been used as references for audio level measurements. The typical reference power level is one milliwatt. Power levels that are measured relative to this reference level are given the designation dBm. However, it is always necessary to be sure of the reference impedance used for such measurements. This can be either explicit, e.g., 0 dBm (600 ), or implicit, if there is certain agreement on what the reference impedance is. Since modern voltmeters have high input impedances, measurements can be made that do not terminate the signal. Therefore, it is not proper to consider this type of measurement a dBm, or power measurement. However, a measurement scale that is designated dBu is now used to measure unterminated voltages. This scale has a voltage reference for 0 dBu that is the same as the voltage required to produce 0 dBm (600 ). Since P = V2/R, the voltage required to create 1 mW into 600 is 0.775 V rms. This is the voltage reference (0 dB) used for dBu measurements without regard to the impedance. The AD8113 operates as a voltage-in, voltage-out device. Therefore, it is easiest to specify all of its parameters in volts, and leave it to the user to convert them to other power units or dB-type measurements as required by the particular application.
CREATING UNITY-GAIN CHANNELS
Unlike audio signals, which have lower bandwidths and longer wavelengths, video signals often use controlled-impedance transmission lines that are terminated in their characteristic impedance. While this is not always the case, there are some considerations when using the AD8113 to route video signals with controlled-impedance transmission lines. Figure 9 shows a schematic of an input and output treatment of a typical video channel.
+5V OR +12V TYPICAL INPUT AD8113 G=2 TYPICAL OUTPUT 75
75 TRANSMISSION LINE 75
75 VIDEO SOURCE
75
-5V OR -12V
Figure 9. Video Signal Circuit
Video signals usually use 75 transmission lines that need to be terminated with this value of resistance at each end. When such a source is delivered to one of the AD8113 inputs, the high input impedance will not properly terminate these signals. Therefore, the line should be terminated with a 75 shunt resistor to ground. Since video signals are limited in their peak-to-peak amplitude, there is no need to attenuate video signals before they pass through the AD8113. The AD8113 outputs are very low impedance and will not properly terminate the source end of a 75 transmission line. In these cases, a series 75 resistor should be inserted at an output that will drive a video signal. Then the transmission line should be terminated with 75 at its far end. This overall termination scheme will divide the amplitude of the AD8113 output by two. An overall unity gain channel is produced as a result of the channel gain-of-two of the AD8113.
Power Considerations of Video Signals
The channels in the AD8113 have a gain of two. This gain is necessary as opposed to a gain of unity in order to restrict the voltage on internal nodes to less than the breakdown voltage. If it is desired to create channels with an overall gain of unity, then a resistive divider at the input will divide the signals by two. After passing through any input/output channel combination of the AD8113, the overall gain will be unity.
+12V AUDIO SOURCE 1k
If the AD8113 is used only to route conventional video signals, runing on analog supplies of 5 V is recommended. This is all that is necessary for video signals because they are limited in their amplitude to generally less than 2 V p-p at the output, after the channel gain-of-two. There will be significant power savings when routing video signals with lower supply voltages. If an AD8113 is used to route a mix of audio and video signals, then other factors must be considered. In general, the analog supplies will be at 12 V to handle the high signal levels required for the audio.
AD8113
1k TYPICAL INPUT G=2 -12V TYPICAL OUTPUT
UNITY GAIN AUDIO OUT
Figure 8. Input Divide Circuit
REV. A
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AD8113
Inputs and outputs should be preassigned to be either audio or video. As described above, audio and video signals are treated differently, so it is difficult to have the same AD8113 inputs or outputs route audio or video signals in the same system at different times. The various audio and video channels should be configured as described in the above sections. Video outputs that drive a terminated 75 transmission line (150 equivalent load) will dissipate significantly more power with 12 V supplies. An upper bound on power dissipation can be approximated by the following method. A video signal at the AD8113 output can have a maximum value of 2 V. This is quite conservative, because most video signals are about 700 mV peak at unity gain or 1.4 V peak after a gain-of-two. A video signal only reaches this level when the video content is at peak white, so this value is even more pessimistic. Finally, a video signal will generally have some kind of sync and blanking interval where its amplitude will be either 0 V (or black) or very close to this level. The power dissipation will be much lower during this period and this will occur at a very regular duty cycle. If the full 2 V signal is assumed to be present at 100% duty cycle at the output, then the current in the output is 2 V/150 = 13.3 mA. If the positive supply is at 12 V, there will be a 10 V drop in the AD8113 output stage from the supply to the output. This yields a power dissipated in the output of 133 mW from one video load when running on supplies of 12 V. This is by far a worst-case situation, and this power dissipation factor can be adjusted lower by adjusting for actual video levels, sync-interval duty cycle, and average picture level considerations. If too much power will be dissipated in this type of configuration, it is possible to lower it by buffering the output. An AD8113 video output drives a divide-by-two resistive divider that is made up of two 1 k resistors. This presents a total load of 2 k to the AD8113 outputs, which significantly reduces the power dissipation. Refer to Figure 10.
+12V TYPICAL INPUT 75 TYPICAL OUTPUT 0.1 F 1k 1k 2 3 + 7 6 75 +5V + 10 F 75 TRANSMISSION LINE 75
CREATING LARGER CROSSPOINT ARRAYS
The AD8113 is a high density building block for creating crosspoint arrays of dimensions larger than 16 x 16. Various features, such as output disable and chip enable, are useful for creating larger arrays. The first consideration in constructing a larger crosspoint is to determine the minimum number of devices required. The 16 x 16 architecture of the AD8113 contains 256 points, which is a factor of 64 greater than a 4 x 1 crosspoint (or multiplexer). The PC board area, power consumption, and design effort savings are readily apparent when compared to using these smaller devices. For a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs. Nonblocking requires that the programming of a given input to one or more outputs does not restrict the availability of that input to be a source for any other outputs. Some nonblocking crosspoint architectures will require more than this minimum as calculated above. Also, there are blocking architectures that can be constructed with fewer devices than this minimum. These systems have connectivity available on a statistical basis that is determined when designing the overall system. The basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to wire-OR the outputs together in the vertical direction. The meaning of horizontal and vertical can best be understood by looking at a diagram. Figure 11 illustrates this concept for a 32 x 32 crosspoint array that uses four AD8113s.
16 IN 00 -15
1k
AD8113
16
AD8113
1k 16 16
16 IN 16 -31
1k
AD8113
1k 16 16
16
AD8113
16 16
AD8113 G=2
-12V
AD8057
- 4
Figure 11. 32 x 32 Audio Crosspoint Array Using Four AD8113s
1k
1k -5V 0.1 F 10 F +
Figure 10. Video Buffer Circuit
After this divider, the signal is now at a unity level because of the channel gain of the AD8113 and the attenuation of the divider. An AD8057 is configured as a gain-of-two buffer to drive the terminated transmission line. The AD8058 is a dual version of the AD8057. The maximum supply voltage of the AD8057 is only about 6 V. If the only system supplies that are available are 12 V, a higher voltage video op amp can be substituted for the AD8057. Good candidates are the AD817 and AD818 or, if dual op amps are needed, the AD826 and AD828.
The inputs are individually assigned to each of the 32 inputs of the two devices and a divider is used to normalize the channel gain. The outputs are wire-ORed together in pairs. The output from only one of a wire-ORed pair should be enabled at any given time. The device programming software must be properly written to cause this to happen. Using additional crosspoint devices in the design can lower the number of outputs that have to be wire-ORed together. Figure 12 shows a block diagram of a system using ten AD8113s to create a nonblocking, gain-of-two, 128 x 16 crosspoint that restricts the wire-ORing at the output to only four outputs. Additionally, by using the lower eight outputs from each of the two Rank 2 AD8113s, a blocking 128 x 32 crosspoint array can be realized. There are, however, some drawbacks to this technique. The offset voltages of the various cascaded devices will accumu-
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REV. A
AD8113
(8 RANK 1 AD8113) 128:32 8 1k IN 00-15 1k 16 RTERM 8 1k IN 16-31 1k
AD8113
8
1k
AD8113
16 RTERM
8
1k
8 1k IN 32-47 1k 16 RTERM 8 1k IN 48-63 1k 16 RTERM 8 1k IN 64 -79 1k 8 1k
AD8113
8
1k
RANK 2 32:16 NONBLOCKING (32:32 BLOCKING) 8 8 1k OUT 00 -15 NONBLOCKING
AD8113
8
1k
AD8113
8
AD8113
16 RTERM
8
1k
8 1k IN 80-95 1k 16 RTERM 8 1k IN 96 -111 1k 16 RTERM 8 1k IN 112 -127 1k 16 RTERM
8 1k 1k 8 1k
8
AD8113
8
AD8113
8
ADDITIONAL 16 OUTPUTS (SUBJECT TO BLOCKING)
AD8113
8
1k
AD8113
8
1k
Figure 12. Nonblocking 128 x 16 Audio Array (128 x 32 Blocking)
late, and the bandwidth limitations of the devices will compound. In addition, the extra devices will consume more current and take up more board space. Once again, the overall system design specifications will determine how to make the various trade-offs.
Multichannel Video and Audio
The good video specifications of the AD8113 make it an ideal candidate for creating composite video crosspoint switches. These can be made quite dense by taking advantage of the AD8113's high level of integration and the fact that composite video requires only one crosspoint channel per system video channel. There are, however, other video formats that can be routed with the AD8113, requiring more than one crosspoint channel per video channel. Some systems use twisted-pair wiring to carry video or audio signals. These systems utilize differential signals and can lower costs because they use lower cost cables, connectors, and termination methods. They also have the ability to lower crosstalk and reject common-mode signals, which can be important for equipment that operates in noisy environments, or where common-mode voltages are present between transmitting and receiving equipment. In such systems, the audio or video signals are differential; there are positive and negative (or inverted) versions of the signals. These complementary signals are transmitted onto each of the two wires of the twisted pair, yielding a first order zero commonmode voltage. At the receive end, the signals are differentially received and converted back into a single-ended signal. REV. A
When switching these differential signals, two channels are required in the switching element to handle the two differential signals that make up the video or audio channel. Thus, one differential video or audio channel is assigned to a pair of crosspoint channels, both input and output. For a single AD8113, eight differential video or audio channels can be assigned to the 16 inputs and 16 outputs. This will effectively form an 8 x 8 differential crosspoint switch. Programming such a device will require that inputs and outputs be programmed in pairs. This information can be deduced through inspection of the programming format of the AD8113 and the requirements of the system. There are other analog video formats requiring more than one analog circuit per video channel. One two-circuit format that is commonly being used in systems such as satellite TV, digital cable boxes, and higher quality VCRs, is called S-video or Y/C video. This format carries the brightness (luminance or Y) portion of the video signal on one channel and the color (chrominance, chroma, or C) on a second channel. Since S-video also uses two separate circuits for one video channel, creating a crosspoint system requires assigning one video channel to two crosspoint channels as in the case of a differential video system. Aside from the nature of the video format, other aspects of these two systems will be the same. Stereo audio can also be routed in a paired-channel arrangement similar to a two-channel video system. -19-
AD8113
There are yet other video formats using three channels to carry the video information. Video cameras produce RGB (red, green, blue) directly from the image sensors. RGB is also the usual format used by computers internally for graphics. RGB can also be converted to Y, R-Y, B-Y format, sometimes called YUV format. These three-circuit video standards are referred to as component analog video. The component video standards require three crosspoint channels per video channel to handle the switching function. In a fashion similar to the two-circuit video formats, the inputs and outputs are assigned in groups of three and the appropriate logic programming is performed to route the video signals.
CROSSTALK
raises the issue that a system's crosstalk is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. It is important to try to separate these two areas when attempting to minimize the effect of crosstalk. In addition, crosstalk can occur among the inputs to a crosspoint and among the outputs. It can also occur from input to output. Techniques will be discussed for diagnosing which part of a system is contributing to crosstalk.
Measuring Crosstalk
Many systems, such as studio audio or broadcast video, that handle numerous analog signal channels, have strict requirements for keeping the various signals from influencing any of the others in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. When there are many signals in close proximity in a system, as will undoubtedly be the case in a system that uses the AD8113, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more AD8113s.
Types of Crosstalk
Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as dB down from the magnitude of the test signal. The crosstalk is expressed by
XT = 20 log10 Asel(s ) Atest(s )
(
)
where s = jw is the Laplace transform variable, Asel(s) is the amplitude of the crosstalk induced signal in the selected channel, and Atest(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to first order). In addition, the crosstalk signal will have a phase relative to the test signal associated with it. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 16 x 16 matrix of the AD8113, look at the number of crosstalk terms that can be considered for a single channel, say the IN00 input. IN00 is programmed to connect to one of the AD8113 outputs where the measurement can be made. First, the crosstalk terms associated with driving a test signal into each of the other 15 inputs can be measured one at a time, while applying no signal to IN00. Then the crosstalk terms associated with driving a parallel test signal into all 15 other inputs can be measured two at a time in all possible combinations, then three at a time, and so on, until, finally, there is only one way to drive a test signal into all 15 other inputs in parallel. Each of these cases is legitimately different from the others and might yield a unique value, depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input. In addition, if the possible combinations and permutations for connecting inputs to the other outputs (not used for measurement) are taken into consideration, the numbers rather quickly grow to astronomical proportions. If a larger crosspoint array of multiple AD8113s is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure all hostile crosstalk; this means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel. In general, this will yield the worst crosstalk number, but this is not always the case, due to the vector nature of the crosstalk signal.
Crosstalk can be propagated by means of any of three methods. These fall into the categories of electric field, magnetic field, and sharing of common impedances. This section will explain these effects. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (e.g., free space) and couples with the receiver and induces a voltage. This voltage is an unwanted crosstalk signal in any channel that receives it. Currents flowing in conductors create magnetic fields that circulate around the currents. These magnetic fields then generate voltages in any other conductors whose paths they link. The undesired induced voltages in these other channels are crosstalk signals. The channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. The power supplies, grounds, and other signal return paths of a multichannel system are generally shared by the various channels. When a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. All these sources of crosstalk are vector quantities, so the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk.
Areas of Crosstalk
A practical AD8113 circuit must be mounted to some sort of circuit board in order to connect it to power supplies and measurement equipment. Great care has been taken to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrinsic device. This, however,
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REV. A
AD8113
Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements will generally be higher than those of more distant channels, so they can serve as a worst-case measure for any other one-channel or two-channel crosstalk measurements.
Input and Output Crosstalk
The flexible programming capability of the AD8113 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. Some examples are illustrative. A given input channel (IN07 in the middle for this example) can be programmed to drive OUT07 (also in the middle). The input to IN07 is just terminated to ground (via 50 or 75 ) and no signal is applied. All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except OUT07 disabled. Since grounded IN07 is programmed to drive OUT07, no signal should be present. Any signal that is present can be attributed to the other 15 hostile input signals, because no other outputs are driven (they are all disabled). Thus, this method measures the all-hostile input contribution to crosstalk into IN07. Of course, the method can be used for other input channels and combinations of hostile inputs. For output crosstalk measurement, a single input channel is driven (IN00, for example) and all outputs other than a given output (IN07 in the middle) are programmed to connect to IN00. OUT07 is programmed to connect to IN15 (far away from IN00), which is terminated to ground. Thus OUT07 should not have a signal present since it is listening to a quiet input. Any signal measured at the OUT07 can be attributed to the output crosstalk of the other 16 hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations.
Effect of Impedances on Crosstalk
On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8113 is specified with excellent differential gain and phase when driving a standard 150 video load, the crosstalk will be higher than the minimum obtainable due to the high output currents. These currents will induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8113. From a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resistor. For low frequencies, the magnitude of the crosstalk is given by XT = 20 log10 ( Mxy x s RL ) where Mxy is the mutual inductance of output X to output Y and RL is the load resistance on the measured output. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing RL. The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length.
PCB Layout
Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas that must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. The packaging of the AD8113 is designed to help keep the crosstalk to a minimum. Each input is separated from each other input by an analog ground pin. All of these AGNDs should be directly connected to the ground plane of the circuit board. These ground pins provide shielding, low impedance return paths, and physical separation for the inputs. All of these help to reduce crosstalk. Each output is separated from its two neighboring outputs by an analog supply pin of one polarity or the other. Each of these analog supply pins provides power to the output stages of only the two nearest outputs. These supply pins provide shielding, physical separation, and a low impedance supply for the outputs. Individual bypassing of each of these supply pins with a 0.01 F chip capacitor directly to the ground plane minimizes high frequency output crosstalk via the mechanism of sharing common impedances. Each output also has an on-chip compensation capacitor that is individually tied to the nearby analog ground pins AGND00 through AGND07. This technique reduces crosstalk by preventing the currents that flow in these paths from sharing a common impedance on the IC and in the package pins. These AGNDxx signals should all be connected directly to the ground plane. The input and output signals will have minimum crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. Vias should be located as close to the IC as possible to carry the inputs and outputs to the inner layer. The input and output signals surface at the input termination resistors and the output series back-termination resistors. To the extent possible, these signals should also be separated as soon as they emerge from the IC package.
The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termination resistors and the loops that drive them. Thus, the PC board on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies the magnitude of the crosstalk will be given by
XT = 20 log10 (RS C M ) x s
[
]
where RS is the source resistance, CM is the mutual capacitance between the test signal circuit and the selected circuit, and s is the Laplace transform variable. From the equation it can be observed that this crosstalk mechanism has a high-pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer.
REV. A
-21-
AD8113
DVCC DGND P1-1 + JUMPER + 0.1 F 10 F 0.1 F 10 F 58 INPUT 00 57,59 AGND 60 INPUT 01 61 AGND 62 INPUT 02 63 AGND 64 INPUT 03 65 AGND 66 INPUT 04 67 AGND 68 INPUT 05 69 AGND 70 INPUT 06 71 AGND 72 75 INPUT 08 75 INPUT 09 75 INPUT 10 75 INPUT 11 75 INPUT 12 75 INPUT 13 75 INPUT 14 75 INPUT 15 75 3,73 INPUT 07 AGND 0.1 F 10 F 1, 75 DVCC P1-2 NC P1-3 AVEE AGND AVCC P1-4 P1-5 P1-6 + NC P1-7 DVCC 0.01 F 21, 55 AVCC AVCC 0.01 F 20, 56 AVEE NO CONNECT: 85-93 AVCC OUTPUT 00 AVEE OUTPUT 01 INPUT 02 75 INPUT 03 75 INPUT 04 75 INPUT 05 75 INPUT 06 75 INPUT 07 AVCC OUTPUT 02 AVEE OUTPUT 03 AVCC OUTPUT 04 AVEE OUTPUT 05 AVCC OUTPUT 06 54 53 0.01 F 52 51 0.01 F 50 49 0.01 F 48 47 0.01 F 46 45 0.01 F 44 43 0.01 F 42 41 0.01 F 40 39 0.01 F 38 37 0.01 F 36 35 0.01 F 34 33 0.01 F 32 31 0.01 F 30 29 0.01 F 28 27 0.01 F 26 25 0.01 F 24 23 0.01 F 22 AVEE 0.01 F
INPUT 00 75 INPUT 01 75
AVCC 75 AVEE 75 AVCC 75 AVEE 75 AVCC 75 AVEE 75 AVCC 75 AVEE 75 AVCC 75 AVEE 75 AVCC 75 AVEE 75 AVCC 75 AVEE 75 AVCC 75 AVEE 75 OUTPUT 15 OUTPUT 14 OUTPUT 13 OUTPUT 12 OUTPUT 11 OUTPUT 10 OUTPUT 09 OUTPUT 08 OUTPUT 07 OUTPUT 06 OUTPUT 05 OUTPUT 04 OUTPUT 03 OUTPUT 02 OUTPUT 01 OUTPUT 00
4 INPUT 08 5 AGND 6 INPUT 09 7 AGND 8 INPUT 10 9 AGND 10 INPUT 11 11 AGND 12 INPUT 12 13 AGND 14 INPUT 13 15 AGND 16 INPUT 14 17 AGND 18 INPUT 15 19 AGND 98 DATA OUT
AD8113
AVEE OUTPUT 07 AVCC OUTPUT 08 AVEE OUTPUT 09 AVCC OUTPUT 10 AVEE OUTPUT 11 AVCC OUTPUT 12 AVEE OUTPUT 13 AVCC OUTPUT 14 AVEE
R 96 R
RESET
DATA IN
UPDATE
OUTPUT 15 AVCC
SER /PAR
P2-5
DGND
CE
A0
A1
A2
A3
D0
D1
D2
D3
P2-2 P2-3
2,74 100
99
97
R C
95 84 83 82 81 80 79 78 77 76
R
D4
P2-4
CLK
94 R33 20k DVCC
P2-1
R
P2-6
P3-1
R
R
R
R
R
R
R
R
R
R
R
SERIAL MODE JUMP
P3-11
P3-12
P3-10
NOTE R = OPTIONAL 50 TERMINATOR RESISTORS C = OPTIONAL SMOOTHING CAPACITOR
Figure 13. Evaluation Board Schematic
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P3-13
P3-14
P3-2
P3-3
P3-4
P3-5
P3-6
P3-7
P3-8
P3-9
REV. A
AD8113
Figure 14. Component Side Silkscreen
Figure 15. Board Layout (Ground Plane)
REV. A
-23-
AD8113
Figure 16. Board Layout (Component Side)
Figure 17. Board Layout (Circuit Side)
-24-
REV. A
AD8113
Figure 18. Board Layout (Signal Layer)
Figure 19. Circuit Side Silkscreen
REV. A
-25-
AD8113
When the AD8113 is optimized for video applications, all signal inputs and outputs are terminated with 75 resistors. Stripline techniques are used to achieve a characteristic impedance on the signal input and output lines, also of 75 . Figure 20 shows a cross-section of one of the input or output tracks along with the arrangement of the PCB layers. It should be noted that unused regions of the four layers are filled up with ground planes. As a result, the input and output traces, in addition to having controlled impedances, are well shielded.
w = 0.008" (0.2mm) TOP LAYER b = 0.0514" (1.3mm) a = 0.008" (0.2mm) t = 0.00135" (0.0343mm) SIGNAL LAYER h = 0.025" (0.63mm) POWER LAYER
RESET CLK CE UPDATE DATA IN
MOLEX 0.100" CENTER CRIMP TERMINAL HOUSING 1
D-SUB 25-PIN (MALE) 14 1
6 DGND MOLEX D-SUB-25 TERMINAL HOUSING SIGNAL 2 3 4 5 6 25 3 1 4 5 2 6 CE RESET UPDATE DATA IN CLK DGND PC 25 13
EVALUATION BOARD
Figure 21. Evaluation Board/PC Connection Cable
BOTTOM LAYER
Figure 20. Cross Section of Input and Output Traces
The board has 32 BNC type connectors: 16 inputs and 16 outputs. The connectors are arranged in a crescent around the device. As can be seen from Figure 16, this results in all 16 input signal traces and all 16 output traces having the same length. This is useful in tests such as all hostile crosstalk tests, where the phase relationship and delay between signals need to be maintained from input to output. There are separate digital (logic) and analog supplies. DVCC should be at 5 V to be compatible with 5 V CMOS and TTL logic. AVCC and AVEE can range from 5 V to 12 V depending on the application. As a general rule, each power supply pin (or group of adjacent power supply pins) should be locally decoupled with a 0.01 F capacitor. If there is a space constraint, it is more important to decouple analog power supply pins before digital power supply pins. A 0.1 F capacitor, located reasonably close to the pins, can be used to decouple a number of power supply pins. Finally a 10 F capacitor should be used to decouple power supplies as they come onto the board.
Controlling the Evaluation Board from a PC
When you launch the crosspoint control software, you will be asked to select the printer port you are using. Most PCs have only one printer port, usually called LPT1. However, some laptop computers use the PRN port. Figure 22 shows the main screen of the control software in its initial reset state (all outputs off). Using the mouse, any input can be connected with one or more outputs by simply clicking on the appropriate radio buttons in the 16 x 16 on-screen array. Each time a button is clicked on, the software automatically sends and latches the required 80-bit data stream to the evaluation board. An output can be turned off by clicking the appropriate button in the off column. To turn off all outputs, click on Reset. While the computer software only supports serial programming via a PC's parallel port and the provided cable, the evaluation board has a connector that can be used for parallel programming. The SER/PAR signal should be at a logic HIGH to use parallel programming. There is no cable or software provided with the evaluation board for parallel programming. These are left to the user to provide. The software offers volatile and nonvolatile storage of configurations. For volatile storage, up to two configurations can be stored and recalled using the Memory 1 and Memory 2 buffers. These function in a fashion identical to the memory on a pocket calculator. For nonvolatile storage of a configuration, the Save Setup and Load Setup functions can be used. This stores the configuration as a data file on disk.
Overshoot on PC Printer Ports' Data Lines
The evaluation board includes Windows(R) based control software and a custom cable that connects the board's digital interface to the printer port of the PC. The wiring of this cable is shown in Figure 21. The software requires Windows 3.1 or later. To install the software, insert the disk labeled Disk #1 of 2 and run the file called SETUP.EXE. Additional installation instructions will be given on-screen. Before beginning installation, it is important to terminate any other Windows applications that are running. Audio signals are not as demanding on termination as are video signals. Therefore, the input terminations can be removed and changed. Likewise, the output series terminations can be shorted or changed in value.
The data lines on some printer ports have excessive overshoot. Overshoot on the pin that is used as the serial clock (Pin 6 on the D-Sub-25 connector) can cause communication problems. This overshoot can be eliminated by connecting a capacitor from the CLK line on the evaluation board to ground. A pad has been provided on the circuit side (C33) of the evaluation board to allow this capacitor to be soldered into place. Depending upon the overshoot from the printer port, this capacitor may need to be as large as 0.01 F.
-26-
REV. A
AD8113
AD8113 Parallel Port Selection
Figure 22. Screen Display and Control Software
REV. A
-27-
AD8113
OUTLINE DIMENSIONS
100-Lead Low Profile Quad Flat Package [LQFP] (ST-100)
Dimensions shown in millimeters
16.00 BSC SQ 1.60 MAX 0.75 0.60 0.45 SEATING PLANE TOP VIEW
(PINS DOWN)
14.00 BSC SQ 12 TYP
100 1 76 75
PIN 1
12.00 REF
1.45 1.40 1.35
10 6 2
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
VIEW A
25 26 51 50
0.15 0.05
SEATING PLANE
0.50 BSC
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026BED
0.27 0.22 0.17
Revision History
Location 4/03--Data Sheet changed from REV. 0 to REV. A. Page
New TPC 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
-28-
REV. A
C02170-0-5/03(A)

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